Regviz

Silicon Labs /MGM240PA32VNN /CMU_S /PCNT0CLKCTRL

Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text

Interpret as PCNT0CLKCTRL

Share

Cut and paste this URL to share the unmodified register and value:

https://regviz.com/r/Silicon Labs/EFR32MG24A120F1536GM48/CMU_S/PCNT0CLKCTRL#0x0

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (DISABLED)CLKSEL

CLKSEL=DISABLED

Description

No Description

Fields

CLKSEL

Clock Select

0 (DISABLED): PCNT0 is not clocked

1 (EM23GRPACLK): EM23GRPACLK is clocking PCNT0

2 (PCNTS0): External pin PCNT_S0 is clocking PCNT0

Links

()

Register Reference

https://github.com/cmsis-svd/cmsis-svd-data